As described in the German technical journal "Siemens Forschungs und Entwicklungs Berichte", Vol. 4 (1975), No. 4, pp 213 to 219, memory circuits employing MNOS-transistors arranged in a matrix and permitting bitwise writing and matrixwise erase are known. These MNOS field-effect transistors with an insulated gate consisting of an Si.sub.3 N.sub.4 partial layer and a silicon-oxide partial layer, are insulated-gate field-effect transistors whose threshold voltages can be shifted between two values U.sub.TL and U.sub.TH with the aid of positive and negative gate voltages. To the two threshold voltages U.sub.TL and U.sub.TH there is assigned the binary status "0" and "1", respectively.
However, insulated-gate field-effect transistors with insulated-gate sequences of different composition are known and such memories have become known as DDC memories (DDC standing for dual-dielectric-cell). Relative thereto, there should be mentioned the MAOS field-effect transistor whose gate oxide comprises one partial layer of aluminum oxide and a second partial layer of silicon oxide. In the following, however, there is used the more general designation DDC memory or DDC field-effect transistor respectively. The mode of operation is described in detail in the above-mentioned reference, and further discussion is not deemed necessary.
According to the "IEEE Journal of Solid-State Circuits" (December 1974), pp. 444 to 446, to permit the bitwise erase of such DDC storage matrices there has been developed a MNOS storage matrix whose MNOS field-effect transistors are arranged on an insulating substrate by being separated from one another on islands, with the substrate regions thereof each comprising a highly doped substrate partial region, and with the substrate partial regions thereof being connected to one another in a column-wise fashion.
In conventional DDC storage matrices, the DDC field-effect transistors are erased or written by applying a voltage of corresponding polarity between the gate and the substrate region, this voltage being sufficient to shift the threshold voltage.
The conventional DDC memory array permitting the bitwise erase, write and read of information in a matrix, however, has the disadvantage that the number of its erasewrite cycles is restricted because the "signal-to-noise ratio" is insufficiently large, i.e. that the magnitude of the gate voltages of the transistors lying in the same row or in the same column with the addressed storage transistor, during the write or erase phase is not low enough to avoid a certain write or erase effect and, consequently, an unwanted reduction of the so-called threshold voltage window.
Moreover, the conventional DDC memory has the disadvantage of being more costly in manufacturing the matrix with the necessary logic circuits on an isolation substrate. It is actually desirable to be able to fabricate such a DDC memory permitting the bitwise erase, including the necessary logic circuits, by employing the conventional planar diffusion technique, also on a semiconducting substrate.